View ADP3207_341872.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

7-Bit Programmable Multiphase Mobile CPU Synchronous Buck Controller ADP3207
FEATURES
1-, 2-, or 3-phase operation at up to 750 kHz per phase 8 mV worst-case differential sensing error over temperature Interleaved PWM outputs for driving external high power MOSFET drivers Automatic power-saving modes maximize efficiency during light load and deeper sleep operation Soft transient control reduces inrush current and audio noise Active current balancing between output phases Independent current limit and load line setting inputs for additional design flexibility Built-in power-good masking supports VID on-the-fly 7-bit digitally programmable 0.3 V to 1.5 V output Overload and short-circuit protection with programmable latch-off delay Built-in clock enable output delays CPU clock until CPU supply voltage stabilizes
EN 1
FUNCTIONAL BLOCK DIAGRAM
VCC
31
VRPM RRPM RT RAMPADJ
12 13 14 15
UVLO SHUTDOWN AND BIAS
ADP3207
OSCILLATOR
CMP
GND 20
TTSENSE 30
+ -
SET EN RESET 1/2/3 - PHASE DRIVER LOGIC RESET
26
PWM1
VRTT 29
THERMAL THROTTLING CONTROL
CURRENT BALANCING CIRCUIT
CMP
+ - +
25
PWM2
CSREF DAC + 200mV CSREF
+ DAC - 300mV -
PGDELAY PWRGD
3 2
DELAY
CURRENT LIMIT CIRCUIT SOFT START
ILIMIT 11
CLKEN
4
COMP
7
Notebook power supplies for next generation Intel(R) processors
GENERAL DESCRIPTION
The ADP32071 is a high efficiency, multiphase, synchronous, buck-switching regulator controller optimized for converting notebook battery voltage into the core supply voltage required by high performance Intel processors. The part uses an internal 7-bit DAC to read voltage identification (VID) code directly from the processor that sets the output voltage. The phase relationship of the output signals can be programmed to provide 1-, 2-, or 3-phase operation, allowing for the construction of up to three interleaved buck-switching stages. The ADP3207 uses a multimode architecture to drive the logiclevel PWM outputs at a programmable switching frequency that can be optimized depending on the output current requirement. The part switches between multiphase and single-phase operation to maximize its effectiveness under all load conditions. In addition, the ADP3207 includes a programmable slope function to adjust the output voltage as a function of the load current. As a result, it is always best positioned for a system transient.
1
PRECISION REFERENCE VID DAC
5 34 35 36 37 38 39 40
FBRTN
VID6
VID5
VID4
VID3
VID2
VID1
Figure 1.
The chip also provides accurate and reliable short-circuit protection, adjustable current limiting, and a delayed powergood output that accommodates on-the-fly output voltage changes requested by the CPU. The ADP3207 is specified over the extended commercial temperature range of 0C to 100C and is available in a 40-lead LFCSP package.
Patent 6,683,441.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
VID0
05782-001
+ -
APPLICATIONS
+ -
SOFT START/ 32 PSI BOOT/ 10 DPRSLP DEEPER SLEEP 9 STSET CONTROL
28 DCM 27 8
+
-
+
-
+
-
1.7V
RESET CMP - CROWBAR
24
PWM3
CURRENT LIMIT
23 22 21 19 18 17
SW1 SW2 SW3 CSCOMP CSSUM CSREF
6 16
FB LLSET
33 DPRSTP
OD
SS
ADP3207 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Test Circuits....................................................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 11 Number of Phases....................................................................... 11 Operation Modes........................................................................ 11 Switch Frequency Setting .......................................................... 12 Output Voltage Differential Sensing ........................................ 12 Output Current Sensing ............................................................ 12 Active Impedance Control Mode............................................. 13 Current Control Mode and Thermal Balance ........................ 13 Voltage Control Mode................................................................ 13 Power-Good Monitoring........................................................... 13 Power-Up Sequence and Soft Start .......................................... 14 Soft Transient .............................................................................. 14 Current-Limit, Short-Circuit, and Latch-Off Protection...... 15 Changing VID on-the-Fly......................................................... 15 Output Crowbar ......................................................................... 16 Reverse Voltage Protection ....................................................... 16 Output Enable and UVLO ........................................................ 16 Thermal Throttling Control ..................................................... 16 Application Information................................................................ 20 Setting the Clock Frequency for PWM Mode........................ 20 Soft-Start and Current-Limit Latch-Off Delay Times ........... 20 PWRGD Delay Timer................................................................ 20 Inductor Selection ...................................................................... 20 COUT Selection ............................................................................. 22 Power MOSFETs......................................................................... 23 Ramp Resistor Selection............................................................ 24 Setting the Switching Frequency for RPM Mode Operation of Phase 1 ......................................................................................... 25 Current-Limit Setpoint.............................................................. 25 Feedback Loop Compensation Design.................................... 25 CIN Selection and Input Current DI/DT Reduction ................ 26 Soft Transient Setting................................................................. 26 Selecting Thermal Monitor Components ............................... 26 Tuning Procedure for ADP3207............................................... 27 Layout and Component Placement ......................................... 28 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30
REVISION HISTORY
1/06--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
ADP3207 SPECIFICATIONS
VCC = 5 V, FBRTN = GND, EN = VCC, VVID = 0.50 V to 1.5000 V, PSI = 1.05 V, DPRSLP = GND, DPRSTP = 1.05 V, LLSET = CSREF, TA = 0C to 100C, unless otherwise noted.1 Table 1.
Parameter VOLTAGE ERROR AMPLIFIER Output Voltage Range2 VID DAC DC Accuracy Load Line Positioning DC Accuracy Differential Nonlinearity2 Line Regulation Input Bias Current Output Current Gain Bandwidth Product Slew Rate LLSET Input Voltage Range2 LLSET Input Bias Current FBRTN Current VID DAC INPUTS Input Low Voltage Input High Voltage Input Current VID Transition Delay Time2 OSCILLATOR Frequency Range2 Frequency Setting Symbol VCOMP VFB - VVID VFB(BOOT) VFB - VVID VFB IFB ICOMP GBW(ERR) VLLSET ILLSET IFBRTN VIL VIH IIN(VID) Conditions Min 0.85 -8 1.192 -78 -1 -1 FB forced to VOUT - 3% COMP = FB CCOMP = 10 pF Relative to CSREF 3 20 25 -200 -100 70 VIDX VIDX VID change to FB change 0.5 0.5 -1 +200 +100 400 0.3 Typ Max 4.0 +8 1.208 -82 +1 +1 Units V mV V mV LSB % A mA MHz V/s mV nA A V V A ns
Measured at FB, relative to VVID, see Figure 2 Measured at end of start-up Measured at FB, relative to VVID, LLSET - CSREF = -80 mV VCC = 4.75 V to 5.25 V
1.200 -80 0.05
0.7 400
fOSC fPHASE
PSI = DPRSTP = 1.05 V, DPRSLP = GND TA = +25C, VVID = 1.2000 V, RT = 215 k TA = +25C, PWM3 = VCC, VVID = 1.2000 V, RT = 215 k TA = +25C, PWM2 = VCC, VVID = 1.2000 V, RT = 215 k IRAMPADJ = 60 A In normal mode In shutdown, or in UVLO, RAMPADJ = 19 V RT = 215 k to GND, VVID = 1.4000 V IVRPM = 0 IVRPM = 120 A VVID = 1.2 V, RT = 215 k VOS(RPM) = VCOMP - VRRPM, PSI = GND CSSUM - CSREF
0.3 155
RAMPADJ Voltage RAMPADJ Input Current Range2 RPM RT Voltage VRPM Reference Voltage RRPM Output Current RPM Comparator Offset CURRENT-SENSE AMPLIFIER Offset Voltage Input Bias Current Gain Bandwidth Product Slew Rate Input Common-Mode Range2 Output Voltage Range2 Output Current
VRAMPADJ IRAMPADJ
0.9 1 -1 1.08 .95 1.0
200 300 600 1.1 60
3 245
1.2 120 +1 1.32 1.05 1.10
MHz kHz kHz kHz V A A V V V A mV mV nA MHz V/s V V A
VRT VVRPM IRRPM VOS(RPM) VOS(CSA) IBIAS(CSSUM) GBW(CSA)
1.2 1 1.03 -5.5 1
-1.0 -50 10 10 0 0.05 470
+1.0 +50
CCSCOMP = 10 pF CSSUM and CSREF ICSCOMP Sinking Current
3.5 2.0
Rev. 0 | Page 3 of 32
ADP3207
Parameter CURRENT BALANCE AMPLIFIER Common Mode Range2 Input Resistance Input Current Input Current Matching Zero Current Switching Threshold Voltage Masked Off-Time CURRENT-LIMIT COMPARATOR ILIMIT Voltage ILIMIT Current Maximum ILIMIT Current2 Current-Limit Threshold Voltage Symbol VSW(X)CM RSW(X) ISW(X) ISW(X) VDCM(SW1) tOFFMSKD VILIMIT IILIMIT VCL Conditions Min -600 30 3 -5 Typ Max +200 60 6 +5 Units mV k A % mV ns 1.75 V A A mV mV mV mV
SWX = 0 V SWX = 0 V SWX = 0 V In DCM mode, DPRSLP = 3.3 V Measured from PWM turn-off RILIMIT = 113 k RILIMIT = 113 k VCSREF - VCSCOMP, RILIMIT = 113 k, PSI = 1.05 V VCSREF - VCSCOMP, RILIMIT = 113 k, 1-phase, (PWM2 = VCC), PSI = GND VCSREF - VCSCOMP, RILIMIT = 113 k, 2-phase, (PWM3 = VCC), PSI = GND VCSREF - VCSCOMP, RILIMIT = 113 k, 3-phase, (neither PWM2 = VCC nor PWM3 = VCC), PSI = GND During start-up, VSS < 1.7 V In normal mode, VSS = 2.0 V In current limit, VSS = 2.0 V During start-up, SS is rising In normal mode In current limit, SS is falling Fast exit from deeper sleep, DPRSLP = 0 V, STSET = VDAC - 0.3 V Slow exit from deeper sleep, DPRSLP = 3.3 V, STSET = VDAC - 0.3 V Slow entry to deeper sleep, DPRSLP = 3.3 V, STSET = VDAC + 0.3 V
40 4.5 -6 350
1.65 -60 180 180 86 55
1.7 -15 192 192 96 64
210 210 107 72
SOFT START TIMER SS Current
ISS
-10 1.5 1.6 1.6
SS Termination Threshold Voltage SS Clamp Voltage Current-Limit Latch-Off Voltage SOFT TRANSIENT CONTROL STSET Current
VTH(SS) VILO(SS) ISOURCE(STSET)
-8 -48 2 1.7 2.9 1.7 -8 -2.5 +2.5
-6 2.5 1.8 1.8
A A A V V V A A A pF mV
Minimum STSET Capacitance2 Long Transient Threshold Accuracy SYSTEM INTERFACE CONTROL INPUTS PSI and DPRSTP Input Low Voltage Input High Voltage DPRSLP and EN Input Low Voltage Input High Voltage THERMAL THROTTLING CONTROL TTSENSE Voltage Range2 TTSENSE VRTT Threshold Voltage TTSENSE VRTT Hysteresis TTSENSE Bias Current VRTT Output Low Voltage VRTT Output High Voltage
CSTSET VOS(SSMASK)
100 VOS(SSMASK) = VSTSET - VDAC 170
VIL VIH VIL VIH
0.7
0.5 0.5 1.3 1.9
0.3
V V V V V V mV A mV V
1.0
2.3 0 2.45 50 -2 4
VCC = 5 V, TTSENSE is falling TTSENSE = 2.6 V IVRTT(SINK) = 400 A IVRTT(SOURCE) = 400 A
2.5 95 10 5
5 2.55 2 500
VOL(VRTT) VOH(VRTT)
Rev. 0 | Page 4 of 32
ADP3207
Parameter POWER-GOOD COMPARATOR Undervoltage Threshold Overvoltage Threshold Output Low Voltage Output Leakage Current Power-Good Delay Timer PGDELAY Threshold PGDELAY Charge Current PGDELAY Discharge Resistance Power-Good Masking Time Crowbar Threshold Voltage Reverse Voltage Detection Threshold Symbol VCSREF(UV) VCSREF(OV) VPWRGD(L) IPWRGD VPGDELAY(TH) IPGDELAY RPGDELAY VCSREF(CB) VCSREF(RV) Conditions Relative to nominal DAC voltage Relative to nominal DAC voltage IPWRGD(SINK) = 4 mA VPWRDG = 5 V Min -240 150 Typ -300 200 85 Max -360 250 250 3 Units mV mV mV A V A s V
VPGDELAY = 2.0 V VPGDELAY = 0.2 V Relative to FBRTN Relative to FBRTN CSREF is falling CSREF is rising 1.65
2.9 1.9 550 130 1.7
1.75
-300 -75 30
-350 -10 400 3
mV mV mV A mV V mV V V mA A V V mV
CLKEN OUTPUT Output Low Voltage Output Leakage Current OD/DCM OUTPUTS Output Low Voltage Output High Voltage PWM OUTPUTS Output Low Voltage Output High Voltage SUPPLY Supply Voltage Range Supply Current VCCOK Threshold Voltage VCC UVLO Threshold Voltage VCC Hysteresis2
1 2
I CLKEN(SINK) = 4 mA V CLKEN = 5 V, VSS = GND VOL VOH VOL(PWM) VOH(PWM) VCC Normal mode EN = 0 V VCC is rising VCC is falling ISINK = 400 A ISOURCE = 400 A IPWM(SINK) = 400 A IPWM(SOURCE) = 400 A
4
10 5 10 5
500
500
4.0 4.5
VCCOK VCCUVLO
4.0
4.2 190 4.4 4.15 260
5.5 10 300 4.5
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). Guaranteed by design or bench characterization, not production tested.
Rev. 0 | Page 5 of 32
ADP3207 TEST CIRCUITS
7-BIT CODE + 40
VID0 VID1 VID2 VID3 VID4 VID5 VID6 DPRSTP PSI VCC
5V 1F 100nF
5V
ADP3207
VCC
31
COMP
7
3.3V
1
1k 10nF
ILIMIT VPRM RRPM RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND
EN PWRGD PGDELAY CLKEN FBRTN FB COMP SS STSET DPRSLP
ADP3207
TTSENSE VRTT DCM OD PWM1 PWM2 PWM3 SW1 SW2 SW3
10k FB
6
LLSET
16
V CSREF
17
113k
1.0V
VDAC
VID DAC
20k
05782-002
VDAC
GND
20
100nF
VFB = FBV = 80mV - FBV = 0mV
Figure 2. Closed-Loop Output Voltage Accuracy Figure 4. Positioning Accuracy
ADP3207
VCC 5V
31
19
CSCOMP
39k
100nF
18
CSSUM
1k
17
CSREF
1.0V
20
VOS = CSCOMP - 1V 40
Figure 3. Current-Sense Amplifier VOS
05782-003
GND
Rev. 0 | Page 6 of 32
05782-004
ADP3207 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter VCC FBRTN SW1 to SW3 RAMPADJ (In Shutdown) All Other Inputs and Outputs Storage Temperature Operating Ambient Temperature Range Operating Junction Temperature Thermal Impedance (JA) Lead Temperature Soldering (10 sec) Infrared (15 sec) Rating -0.3 V to +6 V -0.3 V to +0.3 V -10 V to +25 V -0.3 V to +25 V -0.3 V to VCC + 0.3 V -65C to +150C 0C to 100C 125C 98C/W 300C 260C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute maximum ratings apply individually only, not in combination. Unless otherwise specified, all other voltages are referenced to GND.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 32
ADP3207 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VID6 DPRSTP VID3 VID4 VID0 VID1 VID2 VID5
40 39 38 37 36 35 34 33 32 31
VCC
PSI
EN 1 PWRGD 2 PGDELAY 3 CLKEN 4 FBRTN 5 FB 6 COMP 7 SS 8 STSET 9 DPRSLP 10
30 PIN 1 INDICATOR 29 28
TTSENSE VRTT DCM OD PWM1 PWM2 PWM3 SW1 SW2 SW3
TOP VIEW (Not to Scale)
ADP3207
27 26 25 24 23 22 21
11 12 13 14 15 16 17 18 19 20
ILIMIT
LLSET
RAMPADJ
CSCOMP
VRPM
CSSUM
RRPM
CSREF
GND
RT
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 Mnemonic EN PWRGD PGDELAY CLKEN FBRTN FB COMP SS STSET Description Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low. Power-Good Output. Open drain output that signals when the output voltage is outside of the proper operating range. The pull-high voltage on this pin cannot be higher than VCC. Power-Good Delay Setting Input. A capacitor between this pin and GND sets the power-good delay time. Clock Enable Output. The pull-high voltage on this pin cannot be higher than VCC. Feedback Return. VID DAC and error amplifier reference for remote sensing of the output voltage. Feedback Input. Error amplifier input for remote sensing of the output voltage. Error Amplifier Output and Compensation Point. Soft-Start Delay Setting Input. An external capacitor connected between this pin and GND sets the soft-start ramp-up time and the current-limit latch-off delay time. Soft Transient Slew Rate Timing Input. A capacitor from this pin to GND sets the slew rate of the output voltage when transitioning between the boot voltage and the programmed VID voltage, and when transitioning between active mode and deeper sleep mode. Deeper Sleep Control Input. Current-Limit Setpoint. An external resistor from this pin to GND sets the current-limit threshold of the converter. RPM Mode Reference Voltage Output. RPM Mode Timing Control Input. A resistor between this pin and VRPM sets the RPM mode turn-on threshold voltage. Multiphase Frequency Setting Input. An external resistor connected between this pin and GND sets the oscillator frequency of the device when operating in multiphase PWM mode. PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal PWM ramp. Output Load Line Programming Input. The center point of a resistor divider between CSREF and CSCOMP is connected to this pin to set the load line slope. Current-Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current-sense amplifier and the power-good and crowbar functions. This pin should be connected to the common point of the output inductors. Current-Sense Summing Node. External resistors from each switch node to this pin sum the inductor currents together to measure the total output current. Current-Sense Compensation Point. A resistor and capacitor from this pin to CSSUM determine the gain of the current-sense amplifier and the positioning loop response time. Ground. All internal biasing and the logic output signals of the device are referenced to this ground. Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases should be left open.
Rev. 0 | Page 8 of 32
10 11 12 13 14 15 16 17
DPRSLP ILIMIT VRPM RRPM RT RAMPADJ LLSET CSREF
18 19 20 21 to 23
CSSUM CSCOMP GND SW3 to SW1
05782-005
ADP3207
Pin No. 24 to 26 Mnemonic PWM3 to PWM1 OD DCM VRTT TTSENSE Description Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the ADP3419. Connecting the PWM2 and/or PWM3 outputs to VCC causes that phase to turn off, allowing the ADP3207 to operate as a 1-, 2-, or 3-phase controller. Multiphase Output Disable Logic Output. This pin is actively pulled low when the ADP3207 enters single-phase mode or during shutdown. Connect this pin to the SD inputs of the Phase-2 and Phase-3 MOSFET drivers. Discontinuous Current Mode Enable Output. This pin is actively pulled low when the single-phase inductor current crosses zero. Voltage Regulator Thermal Throttling Logic Output. This pin goes high if the temperature at the monitoring point connected to TTSENSE exceeds the programmed VRTT temperature threshold. Thermal Throttling Sense Input and OVP Disable. The center point of a resistor divider (where the lower resistor is an NTC thermistor) between VCC and GND is connected to this pin to remotely sense the temperature at the desired thermal monitoring point. Grounding TTSENSE disables OVP function. Supply Voltage for the Device. Power State Indicator Input. Pulling this pin to GND forces the ADP3207 to operate in single-phase mode. Deeper Stop Control Input. Voltage Identification DAC Inputs. When in normal operation mode, the DAC output programs the FB regulation voltage from 0.3 V to 1.5 V (see Table 6).
27 28 29 30
31 32 33 34 to 40
VCC PSI DPRSTP VID6 to VID0
Rev. 0 | Page 9 of 32
ADP3207 TYPICAL PERFORMANCE CHARACTERISTICS
2500
250
2000
200
VID = 1.2875V
FREQUENCY (kHz)
1500
VID = 1.1500V
VOLTAGE (mV)
150
3-PHASE PSI = HIGH
1000
VID = 0.8375V
100
2-PHASE PSI = LOW 3-PHASE PSI = LOW
500
05782-006
50
05782-007
0
0
100
200
300 RT (k)
400
500
600
0
100
200
300
400
500 600 RLIMIT (k)
700
800
900
1000
Figure 6. Master Clock Frequency vs. RT
400
Figure 8. Current-Limit Threshold Voltage vs. RLIMIT
350
FREQUENCY (kHz)
300
250
200
05782-008
150
0
0.2
0.4
0.6
0.8 VID (V)
1.0
1.2
1.4
Figure 7. Master Clock vs. VID
Rev. 0 | Page 10 of 32
ADP3207 THEORY OF OPERATION
The ADP3207 combines a multimode PWM/RPM (ramp pulse modulated) control with multiphase logic outputs for use in 1-, 2-, and 3-phase synchronous buck CPU core supply power converters. The internal 7-bit VID DAC conforms to Intel IMVP-6 specifications. Multiphase operation is important for producing the high currents and low voltages demanded by today's microprocessors. Handling high currents in a singlephase converter puts high thermal stress on the system components such as the inductors and MOSFETs. The multimode control of the ADP3207 ensures a stable high performance topology for: * * * * * * * * * * Balancing currents and thermals between phases High speed response at the lowest possible switching frequency and minimal output decoupling Minimizing thermal switching losses due to lower frequency operation Tight load line regulation and accuracy High current output by supporting up to 3-phase operation Reduced output ripple due to multiphase ripple cancellation High power conversion efficiency both at heavy load and light load PC board layout noise immunity Ease of use and design due to independent component selection Flexibility in operation by allowing optimization of design for low cost or high performance The PWM outputs are 5 V logic-level signals intended for driving external gate drivers such as the ADP3419. Because each phase is monitored independently, operation approaching 100% duty cycle is possible. In addition, more than one output can operate at a time to allow overlapping phases.
OPERATION MODES
For ADP3207, the number of phases can be selected by the user as described in the Number of Phases section, or they can dynamically change based on system signals to optimize the power conversion efficiency at heavy and light CPU loads. During a VID transient or at a heavy load condition, indicated by DPRSLP going low and PSI going high, the ADP3207 runs in full-phase mode. All user selected phases operate in interleaved PWM mode that results in minimal VCORE ripple and best transient performance. While in light load mode, indicated by either PSI going low or DPRSLP going high, only Phase 1 of ADP3207 is in operation to maximize power conversion efficiency. In addition to the change of phase number, the ADP3207 dynamically changes operation modes. In multiphase operation, the ADP3207 runs in PWM mode, with switching frequency controlled by the master clock. In single-phase mode based on PSI signal, the ADP3207 switches to RPM mode, where the switching frequency is no longer controlled by the master clock, but by the ripple voltage appearing on the COMP pin. The PWM1 pin is set to high each time the COMP pin voltage rises to a limit determined by the VID voltage and programmed by the external resistor connected between Pin VRPM and Pin RRPM. In single-phase mode based on the DPRSLP signal, the ADP3207 runs in RPM mode, with the synchronous rectifier (low-side) MOSFETs of Phase 1 being controlled by the DCM pin to prevent any reverse inductor current. Thus, the switch frequency varies with the load current, resulting in maximum power conversion efficiency in deeper sleep mode of CPU operation. In addition, during any VID transient, system transient (entry/exit of deeper sleep), or current limit, the ADP3207 goes into full phase mode, regardless of DPRSLP and PSI signals, eliminating current stress to Phase 1. Table 4 summarizes how the ADP3207 dynamically changes phase number and operation modes based on system signals and operating conditions.
NUMBER OF PHASES
The number of operational phases and their phase relationship is determined by internal circuitry that monitors the PWM outputs. Normally, the ADP3207 operates as a 3-phase controller. For 2-phase operation, the PWM3 pin is connected to VCC 5 V programs, and for 1-phase operation, the PWM3 and PWM2 pins are connected to VCC 5 V programs. When the ADP3207 is initially enabled, the controller sinks 50 A on the PWM2 and PWM3 pins. An internal comparator checks the voltage of each pin against a high threshold of 3 V. If the pin voltage is high due to pull up to the VCC 5 V rail, then the phase is disabled. The phase detection is made during the first three clock cycles of the internal oscillator. After phase detection, the 50 A current sink is removed. The pins that are not connected to the VCC 5 V rail function as normal PWM outputs. The pins that are connected to VCC enter into high impedance state.
Rev. 0 | Page 11 of 32
ADP3207
Table 4. Phase Number and Operation Modes
PSI DNC2 1 0 0 DNC2 DNC2
1
DPRSLP DNC2 0 0 0 1 1
VID Transient Period1 Yes No No No No No
Hit Current Limit DNC2 DNC2 No Yes No Yes
No. of Phases Selected by User N 3, 2, or 1 N 3, 2, or 1 DNC2 DNC2 DNC2 DNC2
No. of Phases in Operation N N Phase 1 only N Phase 1 only N
Operation Mode PWM, CCM3 only PWM, CCM3 only RPM, CCM3 only PWM, CCM3 only RPM, automatic CCM3/DCM4 PWM, CCM3 only
VID transient period is the time period following any VID change, including entrance and exit of deeper sleep mode. The duration of VID transient period is the same as that of PWRGD masking time. 2 DNC means do not care. 3 CCM means continuous conduction mode 4 DCM means discontinuous conduction mode.
SWITCH FREQUENCY SETTING
Master Clock Frequency for PWM Mode
The clock frequency of the ADP3207 is set by an external resistor connected from the RT pin to ground. The frequency varies with the VID voltage: the lower the VID voltage, the lower the clock frequency. The variation of clock frequency with VID voltage makes VCORE ripple remain constant and improves power conversion efficiency at a lower VID voltage. Figure 6 shows the relationship between clock frequency and VID voltage, parameterized by RT resistance. To determine the switching frequency per phase, the clock is divided by the number of phases in use. If PWM3 is pulled up to VCC, then the master clock is divided by 2 for the frequency of the remaining phases. If PWM2 and PWM3 are pulled up to VCC, then the switching frequency of a Phase 1 equals the master clock frequency. If all phases are in use, divide by 3.
OUTPUT VOLTAGE DIFFERENTIAL SENSING
The ADP3207 combines differential sensing with a high accuracy, VID DAC, precision REF output and a low offset error amplifier to meet the rigorous accuracy requirement of the Intel IMVP-6 specification. In steady-state, the VID DAC and error amplifier meet the worst-case error specification of 10 mV over the full operating output voltage and temperature range. The CPU core output voltage is sensed between the FB and FBRTN pins. Connect FB through a resistor to the positive regulation point, usually the VCC remote sense pin of the microprocessor. Connect FBRTN directly to the negative remote sense point, the VSS sense point of the CPU. The internal VID DAC and precision voltage reference are referenced to FBRTN, and have a maximum current of 200 A to guarantee accurate remote sensing.
OUTPUT CURRENT SENSING
The ADP3207 provides a dedicated current-sense amplifier (CSA) to monitor the total output current of the converter for proper voltage positioning vs. load current, and for currentlimit detection. Sensing the load current being delivered to the load is inherently more accurate than detecting peak current or sampling the current across a sense element, such as the lowside MOSFET. The current-sense amplifier can be configured several ways depending on system requirements. * * * Output inductor ESR sensing without use of a thermistor for lowest cost Output inductor ESR sensing with use of a thermistor that tracks inductor temperature to improve accuracy Discrete resistor sensing for highest accuracy
Switching Frequency for RPM Mode-Phase 1
When ADP3207 operates in single-phase RPM mode, its switching frequency is not controlled by the master clock, but by the ripple voltage on the COMP pin. The PWM1 pin is set high each time the COMP pin voltage rises to a voltage limit determined by the VID voltage and the external resistance connected between Pin VRPM and Pin RRPM. Whenever PWM1 pin is high, an internal ramp signal rises at a slew rate programmed by the current flowing into the RAMPADJ pin. Once this internal ramp signal hits the COMP pin voltage, the PWM1 pin is reset to low. In continuous current mode, the switching frequency of RPM operation is maintained almost constantly. While in discontinuous current mode, the switching frequency reduces with the load current.
Rev. 0 | Page 12 of 32
ADP3207
The positive input of the CSA is connected to the CSREF pin, which is connected to the output voltage. At the negative input CSSUM pin of the CSA, signals from the sensing element (that is, in case of inductor RDC sensing, signals from the switch node side of the output inductors) are summed together by using series summing resistors. The feedback resistor between CSCOMP and CSSUM sets the gain of the currentsense amplifier, and a filter capacitor is placed in parallel with this resistor. The current information is then given as the voltage difference between CSREF and CSCOMP. This signal is used internally as a differential input for the currentlimit comparator. An additional resistor divider connected between CSREF and CSCOMP with the midpoint connected to LLSET can be used to set the load line required by the microprocessor specification. The current information for load line setting is then given as the voltage difference of CSREF - LLSET. The configuration in the previous paragraph makes it possible for the load line slope to be set independently of the current-limit threshold. In the event that the current-limit threshold and load line do not have to be independent, the resistor divider between CSREF and CSCOMP can be omitted and the CSCOMP pin can be connected directly to LLSET. To disable voltage positioning entirely (that is, to set no load line), tie LLSET to CSREF. To provide the best accuracy for current sensing, the CSA is designed to have a low offset input voltage. In addition, the sensing gain is set by an external resistor ratio. The magnitude of the internal ramp can be set so the transient response of the system becomes optimal. The ADP3207 also monitors the supply voltage to achieve feed-forward control whenever the supply voltage changes. A resistor connected from the power input voltage rail to the RAMPADJ pin determines the slope of the internal PWM ramp. Detailed information about programming the ramp is given in the Ramp Resistor Selection section. External resistors can be placed in series with the SW2 and SW3 pins to create an intentional current imbalance, if desired. Such a condition can exist when one phase has better cooling and supports higher currents than the other phase. Resistor RSW2 and Resistor RSW3 (see the typical application circuit in Figure 10) can be used to adjust thermal balance. It is recommended to add these resistors during the initial design to make sure placeholders are provided in the layout. To increase the current in any given phase, users should make RSW for that phase larger (that is, make RSW = 0 for the hottest phase and do not change it during balance optimization). Increasing RSW to 500 makes a substantial increase in phase current. Increase each RSW value by small amounts to achieve thermal balance starting with the coolest phase. When current limit is reached, the ADP3207 switches to fullphase PWM mode, regardless of System Signal DRPSLP and PSI, to avoid inrush current stress to the Phase 1 power stage.
VOLTAGE CONTROL MODE
A high gain bandwidth error amplifier is used for the voltagemode control loop. The noninverting input voltage is set via the 7-bit VID DAC. The VID codes are listed in Table 6. The noninverting input voltage is offset by the droop voltage as a function of current, commonly known as active voltage positioning. The output of the error amplifier is the COMP pin, which sets the termination voltage for the internal PWM ramps. The negative input, FB, is tied to the output sense location through a resistor, RB, for sensing and controlling the output voltage at the remote sense point. The main loop compensation is incorporated in the feedback network connected between FB and COMP.
ACTIVE IMPEDANCE CONTROL MODE
To control the dynamic output voltage droop as a function of the output current, the signal proportional to the total output current is converted to a voltage that appears between CSREF and LLSET. This voltage can be scaled to equal the droop voltage, which is calculated by multiplying the droop impedance of the regulator with the output current. The droop voltage is then used as the control voltage of the PWM regulator. The droop voltage is subtracted from the DAC reference output voltage and determines the voltage positioning setpoint. The setup results in an enhanced feed-forward response.
CURRENT CONTROL MODE AND THERMAL BALANCE
The ADP3207 has individual inputs for monitoring the current in each phase. The phase current information is combined with an internal ramp to create a current balancing feedback system that is optimized for initial current accuracy and dynamic thermal balance. The current balance information is independent of the total inductor current information used for voltage positioning described in the Active Impedance Control Mode section.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via the CSREF pin. The PWRGD pin is an open drain output that can be pulled up through an external resistor to a voltage rail that is not necessarily the same VCC voltage rail of the controller. Logic high level indicates that the output voltage is within the voltage limits defined by a window around the VID voltage setting. PWRGD goes low when the output voltage is outside of that window.
Rev. 0 | Page 13 of 32
ADP3207
Following the IMVP-6 specification, PWRGD window is defined as -300 mV below and +200 mV above the actual VID DAC output voltage. For any DAC voltage below 300 mV, only the upper limit of the PWRGD window is monitored. To prevent false alarm, the power-good circuit is masked during various system transitions, including any VID change and entrance/exit out of deeper sleep. The duration of the PWRGD mask is set by an internal timer to be about 100 s. In conditions where a larger than 200 mV voltage drop occurs during deeper sleep entry or slow deeper sleep exit, the duration of PWRGD masking is extended by an internal logic circuit.
VCC
EN
2.9V
SS
1.2V
1.7V
POWER-UP SEQUENCE AND SOFT START
The power-on ramp-up time of the output voltage is set with a capacitor tied from the SS pin to GND. The capacitance on the SS pin also determines the current-limit latch-off time as explained in the Soft Transient section. The whole power-up sequence, including soft start, is illustrated in Figure 9. In VCC UVLO or in shutdown, the SS pin is held at zero potential. When VCC ramps above the upper UVLO threshold and EN is asserted high, the ADP3207 enables internal bias and starts a reset cycle that lasts about 50 s to 60 s. Next, when initial reset is over, the chip detects the number of phases set by the user, and gives a go signal to ramp up the SS voltage. During soft start, the external SS capacitor is charged by an internal 8 A current source. The VCORE voltage follows the ramping SS voltage up to the VBOOT voltage level, which is determined by a burnt-in VID code (the 1.2 V code by IMVP-6 specification). While VCORE is being regulated at VBOOT voltage, the SS capacitor continues to rise. When the SS pin voltage reaches 1.7 V, the ADP3207 asserts the CLKEN signal low, given that the VCORE voltage is within the power-good window of VBOOT. The ADP3207 reads the VID codes provided by the CPU on VID0 to VID6 input pins. The VCORE voltage changes from VBOOT to the VID voltage by a well controlled soft transition, as introduced in the Soft Transient section. Meanwhile, the SS pin voltage is quickly charged up to a clamp voltage of 2.9 V. The PWRGD signal is not asserted until there is a tCPU_PWRGD delay of about 3 ms to 10 ms as specified by the IMVP-6. The power-good delay can be programmed by the capacitor connected from PGDELAY to GND. Before the CLKEN signal is asserted low, PGDELAY is reset to zero. After the assertion of the CLKEN signal, an internal source current of 2 A starts charging up the external capacitor on the PGDELAY pin. Assuming the VCORE voltage is settled within the power-good window defined by the VID DAC voltage, the PWRGD signal is asserted high when the PGDELAY voltage reaches the 2.9 V power-good delay termination threshold. If either EN is taken low or VCC drops below the lower VCC UVLO threshold, then both the SS capacitor and PGDELAY capacitor are reset to ground to be ready for another soft-start cycle.
VCORE
VBOOT
VVID
CLKEN
PWRGD
Figure 9. Power-Up Sequence
SOFT TRANSIENT
The ADP3207 provides a soft transient function to reduce inrush current during various transitions, including the entrance/exit of deeper sleep and the transition from VBOOT to VID voltage. Reducing the inrush current helps decrease the acoustic noise generated by the MLCC input capacitors and inductors. The soft transient feature is implemented with an STSET buffer amplifier that outputs constant sink or source current on the STSET pin where an external capacitor is connected. The capacitor is used to program the slew rate of VCORE voltage during any VID voltage transient. During steady-state operation, both the reference input of the voltage error amplifier and the STSET amplifier are connected to the VID DAC output. Consequently, the STSET voltage is a buffered version of VID DAC output. When system signals trigger a soft transition, the reference input of the voltage error amplifier switches from the DAC output to the STSET output, while the input of the STSET amplifier remains connected to the DAC. The STSET buffer input sees the almost instantaneous VID voltage change and tries to track it. Tracking is not instantaneous because the buffer slew rate is limited by the source/sink current capability of the STSET output. Therefore, VCORE voltage follows the VID DAC output voltage change with a controlled slew rate. When the transient period is complete, the reference input of the voltage amplifier switches back to the VID DAC output to ensure higher accuracy.
Rev. 0 | Page 14 of 32
05782-009
tCPU_PWRGD
ADP3207
Table 5 lists the source/sink current on the STSET pin for various transitions. By charging/discharging the external capacitor on the STSET pin, users actually program the voltage slew rate on the STSET pin, and consequently, on the VCORE output. For example, a 750 pF STSET capacitor leads to a 10 mV/s VCORE slew rate appropriate for a fast exit from deeper sleep, and to a 3.3 mV/s VCORE slew rate for a slow entry to, or exit from, deeper sleep. Table 5. Source/Sink Current of STSET
VID Transient Entrance to Deeper Sleep Fast Exit from Deeper Sleep Slow Exit from Deeper Sleep Transient from VBOOT to VID
1
An inherent per phase current limit protects individual phases in case one or more phases stop functioning because of a faulty component. This limit is based on the maximum normal-mode COMP voltage. After a current limit is hit, or following a PWRGD failure, the SS pin is discharged by an internal sink current of 2 A. A comparator monitors the SS pin voltage and shuts off the controller when the voltage drops below about 1.65 V. Because voltage ramp (2.9 V - 1.65 V = 1.25 V) and discharge current (2 A) are internally fixed, current-limit latch-off delay time can be set by selecting the external SS pin capacitor. The controller keeps cycling the phases during latch-off delay time. If current overload is removed and PWRGD is recovered before the 1.65 V threshold is reached, then the controller resumes normal operation, and the SS pin voltage recovers to 2.9 V clamp level. The latch-off can be reset by removing and reapplying VCC, or by recycling the EN pin low and high for a short time. To disable the current-limit latch-off function, an external pull-up resistor can be tied from the SS pin to the VCC rail. The pull-up current has to override the 2 A sink current of the SS pin to prevent the SS capacitor from discharging down to the 1.65 V latch-off threshold.
System Signals DPRSLP DPRSTP HIGH LOW HIGH DNC1 DNC1 DNC1 HIGH DNC1
STSET Current -2.5 A +7.5 A +2.5 A 2.5 A
Do not care.
CURRENT-LIMIT, SHORT-CIRCUIT, AND LATCHOFF PROTECTION
The ADP3207 compares the differential output of a currentsense amplifier to a programmable current-limit setpoint to provide current-limiting function. The nominal voltage on the ILIMIT pin is 1.7 V. The current-limit threshold is set with a resistor connected from the ILIMIT pin to GND. In multiphase normal operating mode, the ILIMIT is internally scaled by using a trimmed 12 k resistor to give a current-limit threshold of 10 mV for each A of ILIMIT current. For single-phase operation, the current-limit threshold is scaled down even further. The scaling factor is the user selected number of phases. For example, a 3-phase design scales the current-limit threshold to 3.3 mV/A referred to single-phase operation; a 2-phase design scales the current-limit threshold to 5 mV/A also referred to single-phase operation. During any mode of operation, if the voltage difference between CSREF and CSCOMP rises above the current-limit threshold, the internal current-limit amplifier takes control over the internal COMP voltage to maintain an average output current equal to the set limit level. During start-up when the output voltage is below 200 mV, a secondary current limit is activated. This is necessary because the voltage swing on CSCOMP cannot extend below ground. The secondary current-limit circuit clamps the internal COMP voltage and sets the internal compensation ramp termination voltage at 1.5 V level. The clamp actually limits voltage drop across the low side MOSFETs through the current balance circuitry.
CHANGING VID ON-THE-FLY
The ADP3207 is designed to track dynamically changing VID code. As a result, the converter output voltage, that is, the CPU VCC voltage, can change without the need to reset either the controller or the CPU. This concept is commonly referred to as VID on-the-fly (VID OTF) transient. A VID-OTF can occur either under light load or heavy load conditions. The processor signals the controller by changing the VID inputs in LSB incremental steps from the start code to the finish code. The change can be either upwards or downwards steps. When a VID input changes state, the ADP3207 detects the change but ignores the new code for a minimum of time of 400 ns. This keep out is required to prevent reaction to false code that can occur by a skew in the VID code while the 7-bit VID input code is in transition. Additionally, the VID change triggers a PWRGD masking timer to prevent a PWRGD failure. Each VID change resets and retriggers the internal PWRGD masking timer. As listed in Table 5, during any VID transient, the ADP3207 forces a multiphase PWM mode regardless of system input signals.
Rev. 0 | Page 15 of 32
ADP3207
OUTPUT CROWBAR
To protect the CPU load and output components of the converter, the PWM outputs are driven low, DCM and OD are driven high (that is, commanded to turn on the low-side MOSFETs of all phases) when the output voltage exceeds an OVP threshold of 1.7 V as specified by IMVP-6. Turning on the low-side MOSFETs discharges the output capacitor as soon as reverse current builds up in the inductors. If the output overvoltage is due to a short of the high-side MOSFET, then this crowbar action current limits the input supply or causes the input rail fuse to blow, protecting the microprocessor from destruction. Once overvoltage protection (OVP) is triggered, the ADP3207 is latched off. The latch-off function can be reset by removing and reapplying VCC, or by recycling EN low and high for a short time. OVP can be disabled by grounding the TTSENSE pin. The OVP comparator monitors the output voltage via the CSREF pin. MOSFETs are turned off by setting both DCM and OD low. DCM and OD pins are set high again when CSREF voltage recovers above -100 mV.
OUTPUT ENABLE AND UVLO
The VCC supply voltage to the controller must be higher than the UVLO upper threshold, and the EN pin must be higher than its logic threshold so the ADP3207 can begin switching. If the VCC voltage is less than the UVLO threshold, or the EN pin is logic low, then the ADP3207 is in shutdown. In shutdown, the controller holds the PWM outputs at ground, shorts the SS pin and PGDELAY pin capacitors to ground, and drives DCM and OD pins low. Proper power supply sequencing during start-up and shutdown of the ADP3207 must be adhered to. All input pins must be at ground prior to applying or removing VCC. All output pins should be left in high impedance state while VCC is off.
REVERSE VOLTAGE PROTECTION
Very large reverse currents in inductors can cause negative VCORE voltage, which is harmful to the CPU and other output components. ADP3207 provides reverse voltage protection (RVP) function without additional system cost. The VCORE voltage is monitored through the CSREF pin. Any time the CSREF pin voltage is below -300 mV, the ADP3207 triggers its RVP function by disabling all PWM outputs and setting both DCM and OD pins low. Thus, all the MOSFETs are turned off. The reverse inductor current can be quickly reset to zero by dumping the energy built up in the inductor into the input dc voltage source via the forward-biased body diode of the highside MOSFETs. The RVP function is terminated when the CSREF pin voltage returns above -100 mV. Occasionally, overvoltage crowbar protection results in negative VCORE voltage, because turn-on of all low-side MOSFETs leads to very large reverse inductor current. To prevent damage of the CPU by negative voltage, ADP3207 keeps its RVP monitoring function alive even after OVP latch-off. During OVP latch-off, if the CSREF pin voltage drops below -300mV, then all low-side
THERMAL THROTTLING CONTROL
The ADP3207 includes a thermal monitoring circuit to detect if the temperature of the variable resistor (VR) has exceeded a user-defined thermal throttling threshold. The thermal monitoring circuit requires an external resistor divider connected between the VCC pin and GND. The divider consists of an NTC thermistor and a resistor. To generate a voltage that is proportional to temperature, the midpoint of the divider is connected to the TTSENSE pin. Whenever the temperature trips the set alarm threshold, an internal comparator circuit compares the TTSENSE voltage to a half VCC threshold and outputs a logic level signal at the VRTT output. The VRTT output is designed to drive an external transistor that, in turn, provides the high current, open drain VRTT signal that is required by the IMVP-6 specification. When the temperature is around the set alarm point, the internal VRTT comparator has a hysteresis of about 100 mV to prevent high frequency oscillation of VRTT. The TTSENSE pin also serves the function of disabling OVP. In extreme heat, users should make sure that the TTSENSE pin voltage remains above 1 V if OVP is desired.
Rev. 0 | Page 16 of 32
ADP3207
Table 6. VID Code Table
VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 OUTPUT 1.5000 V 1.4875 V 1.4750 V 1.4625 V 1.4500 V 1.4375 V 1.4250 V 1.4125 V 1.4000 V 1.3875 V 1.3750 V 1.3625 V 1.3500 V 1.3375 V 1.3250 V 1.3125 V 1.3000 V 1.2875 V 1.2750 V 1.2625 V 1.2500 V 1.2375 V 1.2250 V 1.2125 V 1.2000 V 1.1875 V 1.1750 V 1.1625 V 1.1500 V 1.1375 V 1.1250 V 1.1125 V 1.1000 V 1.0875 V 1.0750 V 1.0625 V 1.0500 V 1.0375 V 1.0250 V 1.0125 V 1.0000 V 0.9875 V 0.9750 V 0.9625 V 0.9500 V 0.9375 V 0.9250 V 0.9125 V 0.9000 V 0.8875 V 0.8750 V VID6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID3 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT 0.8625 V 0.8500 V 0.8375 V 0.8250 V 0.8125 V 0.8000 V 0.7875 V 0.7750 V 0.7625 V 0.7500 V 0.7375 V 0.7250 V 0.7125 V 0.7000 V 0.6875 V 0.6750 V 0.6625 V 0.6500 V 0.6375 V 0.6250 V 0.6125 V 0.6000 V 0.5875 V 0.5750 V 0.5625 V 0.5500 V 0.5375 V 0.5250 V 0.5125 V 0.5000 V 0.4875 V 0.4750 V 0.4625 V 0.4500 V 0.4375 V 0.4250 V 0.4125 V 0.4000 V 0.3875 V 0.3750 V 0.3625 V 0.3500 V 0.3375 V 0.3250 V 0.3125 V 0.3000 V 0.2875 V 0.2750 V 0.2625 V 0.2500 V 0.2375 V
Rev. 0 | Page 17 of 32
ADP3207
VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 0 0 0 0 0 0 0 0 0 0 1 1 1 VID3 0 0 1 1 1 1 1 1 1 1 0 0 0 VID2 1 1 0 0 0 0 1 1 1 1 0 0 0 VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 OUTPUT 0.2250 V 0.2125 V 0.2000 V 0.1875 V 0.1750 V 0.1625 V 0.1500 V 0.1375 V 0.1250 V 0.1125 V 0.1000 V 0.0875 V 0.0750 V VID6 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUTPUT 0.0625 V 0.0500 V 0.0375 V 0.0250 V 0.0125 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V 0.0000 V
Rev. 0 | Page 18 of 32
ADP3207
10F / 25V x 8 VDC + C1 C8
1 2
+ D3 1N4148 R6* IN SD SW 8 DRVL 6 U3 ADP3419 Q3 IRF7832 CROWBAR GND 7 VCC DRVH 9 Q1 IRF7821 BST 10 C15 1F
VDC RTN
RTH1 100k, 5% NTC
4 5
C9 10nF C14 4.7F
3 DRVLSD
C16 1nF 330F / 4V x 6 Q2 PANASONIC SP SERIES IRF7821 L1 9mW EACH 490nH/0.85mW + Q4 IRF7832 C20 + C25
VCC (CORE) 0.3V - 1.5V 40A
V5S
10F x 30 MLCC IN AND AROUND SOCKET
R7*
1
DPRS LPVR VR_ON IMVP6_PWRGD C11 1F R1 3k RR 280k 1% V3_3S FROM CPU VRTT# R2 3k
IN
2 3 4 5
BST 10 SD DRVLSD CROWBAR VCC C17 4.7F DRVH 9 SW 8 GND 7 DRVL 6 U2 ADP3419
C18 1F
C19 1nF
Q6 IRF7821 L2 490nH/0.85mW Q5 IRF7821 RTH2 220k , 5% NTC Q7 IRF7832 Q8 IRF7832
VSS (SENSE)
40 1 EN PWRGD PGDELAY CLKEN FBRTN FB COMP SS STSET DPRSLP TTSENSE VRTT DCM OD PWM1 PWM2 PWM3 SW1 SW2 SW3
CPGDLY 4.7nF CLKEN CB 330pF RA RB CA 1.67k 220pF 59.0k 1% 1% CSS 12nF RLIM 133k 1% RRPM 576k 1% RT 127k 1% CFB 18pF
ILIMIT VRPM RRPM RT RAMPADJ LLSET CSREF CSSUM CSCOMP GND
RSW1* RSW2* RPH2 84.5k 1% RCS1 RCS2 73.2k 165k CCS1 1.8nF C12 1nF CCS2 2nF
RPH1 84.5k 1%
CSTSET 390pF
C13 1nF
R5 1
* FOR A DESCRIPTION OF OPTIONAL COMPONENTS, SEE THE THEORY OF OPERATION SECTION
05782-010
Rev. 0 | Page 19 of 32
U1 ADP3207
R4 6.81k 1%
Figure 10. Typical 2-Phase Application Circuit
R3 10k D3 1N4148
VCC (SENSE)
VID0 VID1 VID2 VID3 VID4 VID5 VID6 DPRST P PSI VCC
ADP3207 APPLICATION INFORMATION
The design parameters for a typical Intel IMVP6-compliant CPU Core VR application are as follows: * * * * * * * * * * * Maximum input voltage (VINMAX) = 19 V Minimum input voltage (VINMIN) = 7 V Output voltage by VID setting (VVID) = 1.150 V Maximum output current (IO) = 44 A Load line slope (RO) = 2.1 m Maximum output current step (IO) = 34.5 A Maximum output thermal current (IOTDC) = 32 A Number of phases (n) = 2 Switching frequency per phase (fSW) = 280 kHz Duty cycle at maximum input voltage (DMIN) = 0.061 Duty cycle at minimum input voltage (DMAX) = 0.164
C SS = 8 A x t SS VBOOT
(2)
where: VBOOT is the boot voltage for the CPU, defined in the IMVP-6 specification as 1.2 V. tSS is the desired soft-start time, recommended to be below 3 ms in the IMVP-6 specification. Assuming a desired soft-start time of 2 ms, CSS is 13.3 nF, with the closest standard capacitance at 12 nF. Once CSS has been chosen, the current-limit latch-off time is equal to 7.2 ms according to the following calculation:
t DELAY = 1.2 V x C SS 2 A
(3)
PWRGD DELAY TIMER
The PWRGD delay, tCPU_PWRGD, is defined in the IMVP-6 specification as the time period between the CLKEN assertion and the PWRGD assertion. It is programmed by a cap on the PGDELAY pin.
C PGDLY = 1.9 A x t CPU _ PWRGD 2.9 V
SETTING THE CLOCK FREQUENCY FOR PWM MODE
In PWM mode operation, The ADP3207 uses a fixed-frequency control architecture. The frequency is set by an external timing resistor (RT). The clock frequency and the number of phases determine the switching frequency per phase, which directly relates to switching losses, and the sizes of the inductors and input and output capacitors. In a 2-phase design, a clock frequency of 560 kHz sets the switching frequency to 280 kHz per phase. This selection represents a trade-off between the switching losses and the minimum sizes of the output filter components. To achieve a 560 kHz oscillator frequency at VID voltage 1.150 V, RT has to be 237 k. Alternatively, the value for RT can be calculated using
RT = VVID + 1.0 V n x f SW x 16 pF - 5 k
(4)
The IMVP-6 specifies that the PWRGD delay is between 3 ms to 20 ms. Assuming 7 ms PWRGD delay is preferred, then CPGDLY is 4.7 nF.
INDUCTOR SELECTION
The choice of inductance determines the ripple current in the inductor. Less inductance leads to more ripple current, which increases the output ripple voltage and conduction losses in the MOSFETs. However, this allows the use of smaller-size inductors, and for a specified peak-to-peak transient deviation, it allows less total output capacitance. Conversely, a higher inductance means lower ripple current and reduced conduction losses, but requires larger size inductors and more output capacitance for the same peak-to-peak transient deviation. In a multiphase converter, the practical peak-to-peak inductor ripple current is less than 50% of the maximum dc current in the same inductor. Equation 5 shows the relationship between the inductance, oscillator frequency, and peak-to-peak ripple current. Equation 6 can be used to determine the minimum inductance based on a given output ripple voltage.
IR = VVID x (1 - D MIN ) f SW x L
(1)
where 16 pF and 25 k are internal IC component values. For good initial accuracy and frequency stability, it is recommended to use a 1% resistor.
SOFT-START AND CURRENT-LIMIT LATCH-OFF DELAY TIMES
The soft-start and current-limit latch-off delay functions share the SS pin. Consequently, these two parameters must be considered together. The first step is to set CSS for the soft-start ramp. This ramp is generated with a 8 A internal current source. The value for CSS can be set as
(5) (6)
L
VVID x R O x (1 - (n x D MIN ))x (1 - D MIN ) f SW x V RIPPLE
Rev. 0 | Page 20 of 32
ADP3207
Solving Equation 6 for a 20 mV peak-to-peak output ripple voltage yields
L 1.150 V x 2.1 m x (1 - (2 x 0.061)) x (1 - 0.061) 280 kHz x 20 mV = 356 nH
Output Droop Resistance
The inductor design requires that the regulator output voltage measured at the CPU pins drops when the output current increases. The specified voltage drop corresponds to a dc output resistance (RO). The output current is measured by summing the currents of the resistors monitoring the voltage across each inductor and by passing the signal through a low-pass filter. This summer-filter is implemented by the CS amplifier that is configured with resistors RPH(X) (summer), and RCS and CCS (filter). The output resistance of the regulator is set by the following equations, where RL is the DCR of the output inductors:
RO =
CCS =
If the ripple voltage ends up being less than the initially selected value, then the inductor can be changed to a smaller value until the ripple value is met. This iteration allows optimal transient response and minimum output decoupling. The smallest possible inductor should be used to minimize the number of output capacitors. For this example, choosing a 360 nH inductor is a good starting point, and gives a calculated ripple current of 10.7 A. The inductor should not saturate at the peak current of 27.4 A, and should be able to handle the sum of the power dissipation caused by the average current of 16 A in the winding and core loss. Another important factor in the inductor design is the DCR, which is used to measure phase currents. A large DCR causes excessive power losses, though too small a value leads to increased measurement error. This example uses an inductor with a DCR of 0.89 m.
RCS x RL R PH ( X )
L R L x RCS
(7) (8)
Selecting a Standard Inductor
Once the inductance and DCR are known, the next step is to either design an inductor or select a standard inductor that comes as close as possible to meeting the overall design goals. It is also important to have the inductance and DCR tolerance specified to keep the accuracy of the system controlled; 20% inductance and 15% DCR (at room temperature) are reasonable assumptions that most manufacturers can meet.
Users have the flexibility of choosing either RCS or RPH(X). Due to the current drive ability of the CSCOMP pin, the RCS resistance should be larger than 100 k. For example, users should initially select RCS to be equal to 220 k, then use Equation 8 to solve for CCS
CCS = 360 nH 0.89 m x 220 k = 1.84 nF
Because CCS is not the standard capacitance, it is implemented with two standard capacitors in parallel: 1.8 nF and 47 pF. For the best accuracy, CCS should be a 5% NPO capacitor. Next, solve RPH(X) by rearranging Equation 7.
RPH ( X ) 0.89 m 2 .1 m
Power Inductor Manufacturers
The following companies provide surface mount power inductors optimized for high power applications upon request: * * * * Vishay Dale Electronics, Inc. http://www.vishay.com Panasonic http://www.panasonic.com Sumida Corporation http://www.sumida.com NEC Tokin Corporation http://www.nec-tokin.com
x 220 k = 93.2 k
The standard 1% resistor for RPH(X) is 93.1 k.
Inductor DCR Temperature Correction
With the inductor DCR used as a sense element, and copper wire being the source of the DCR, users need to compensate for temperature changes in the inductor's winding. Fortunately, copper has a well-known temperature coefficient (TC) of 0.39%/C. If RCS is designed to have an opposite sign but equal percentage change in resistance, then it cancels the temperature variation of the inductor DCR. Due to the nonlinear nature of NTC thermistors, series resistors, RCS1 and RCS2 (see Figure 11) are needed to linearize the NTC and produce the desired temperature coefficient tracking.
Rev. 0 | Page 21 of 32
ADP3207
PLACE AS CLOSE AS POSSIBLE TO NEAREST INDUCTOR TO OR LOW-SIDE MOSFET SWITCH RTH NODES ADP3207 TO VOUT SENSE
5.
Calculate RTH = RTH x RCS, then select the closest value of thermistor that is available. Also, compute a scaling factor k based on the ratio of the actual thermistor value relative to the computed one
k= RTH ( ACTUAL) RTH (CALCULATED)
RPH1 CSCOMP
18
RPH2
RPH3
(11)
RCS1 CCS
RCS2 KEEP THIS PATH AS SHORT AS POSSIBLE AND WELL AWAY FROM SWITCH NODE LINES
CSSUM
6.
Finally, calculate values for RCS1 and RCS2 using
RCS 2 = RCS x ((1 - k ) + (k x rCS 2 )) RCS1 = RCS x k x rCS1
17
16
05782-011
CSREF
(12)
Figure 11. Temperature Compensation Circuit Values
The following procedure and equations yield values for RCS1, RCS2, and RTH (the thermistor value at 25C) for a given RCS value: 1. Select an NTC to be used based on type and value. Because there is no value yet, start with a thermistor with a value close to RCS. The NTC should also have an initial tolerance of better than 5%. Based on the type of NTC, find its relative resistance value at two temperatures. Temperatures that work well are 50C and 90C. These are called Resistance Value A (A is RTH(50C)/RTH(25C)) and Resistance Value B (B is RTH(90C)/RTH(25C)). Note that the relative value of NTC is always 1 at 25C. Next, find the relative value of RCS that is required for each of these temperatures. This is based on the percentage of change needed, which is initially 0.39%/C. These are called r1 and r2.
1 1 + TC x (T1 - 25) 1 r2 = 1 + TC x (T2 - 25) r1 =
This example starts with a thermistor value of 100 k and uses a Vishay NTHS0603N04 NTC thermistor (a 0603 size thermistor) with A = 0.3359 and B = 0.0771. From this data, rCS1 = 0.359, rCS2 = 0.729 and rTH = 1.094. Solving for RTH yields 240 k, so 220 k is chosen, making k = 0.914. Finally, RCS1 and RCS2 are 72.3 k and 166 k. Choosing the closest 1% resistor values yields a choice of 71.5 k and 165 k.
COUT SELECTION
The required output decoupling for processors and platforms is typically recommended by Intel. The following guidelines can also be used if both bulk and ceramic capacitors in the system: * Select the total amount of ceramic capacitance. This is based on the number and type of capacitors to be used. The best location for ceramics is inside the socket; 20 pieces of Size 0805 being the physical limit. Additional capacitors can be placed along the outer edge of the socket. Select the number of ceramics and find the total ceramic capacitance (CZ). Combined ceramic values of 200 F to 300 F are recommended and are usually made up of multiple 10 F or 22 F capacitors. Note that there is an upper limit imposed on the total amount of bulk capacitance (CX) when considering the VID on-the-fly output voltage stepping (voltage step VV in time tV with error of VERR), and also a lower limit based on meeting the critical capacitance for load release at a given maximum load step IO. For a step-off load current, the current version of the IMVP-6 specification allows a maximum VCORE overshoot (VOSMAX) of 10 mV, plus 1.5% of the VID voltage. For example, if the VID is 1.150 V, then the largest overshoot allowed is 27 mV.
L x I O VOSMAX n x RO + I O - Cz
2.
3.
*
(9)
*
where: TC = 0.0039 T1 = 50C T2 = 90C. 4. Compute the relative values for rCS1, rCS2, and rTH using
rCS 2 = rCS1 =
rTH
A 1 - 1 - rCS 2 r1 - rCS 2 1 = 1 1 - 1 - rCS 2 rCS1
( A - B ) x r1 x r2 - A x (1 - B ) x r2 + B x (1 - A ) x r1 A x (1 - B ) x r1 - B x (1 - A ) x r2 - ( A - B ) (1 - A )
(10)
C x ( MIN )
x VVID
(13)
C X ( MAX )
2 V nKRO L V - 1 - C z x V x 1 + t v VID x 2 V nK 2 RO VVID L V
(14)
Rev. 0 | Page 22 of 32
ADP3207
where:
V K = -1n ERR V V
POWER MOSFETS
(15) For normal 20 A per phase application, the N-channel power MOSFETs are selected for two high-side switches and two lowside switches per phase. The main selection parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS and RDS(ON). Because the gate drive voltage (the supply voltage to the ADP3419) is 5 V, logic-level threshold MOSFETs must be used. The maximum output current IO determines the RDS(ON) requirement for the low-side (synchronous) MOSFETs. In the ADP3207, currents are balanced between phases; the current in each low-side MOSFET is the output current divided by the total number of MOSFETs (nSF). With conduction losses being dominant, the following equation shows the total power dissipated in each synchronous MOSFET in terms of the ripple current per phase (IR) and average total output current (IO):
I PSF = (1 - D ) x O nSF 1 n x IR + x 12 n SF
2 2
To meet the conditions of these equations and transient response, the ESR of the bulk capacitor bank (RX) should be less than two times the droop resistance, RO. If the CX(MIN) is larger than CX(MAX), the system does not meet the VID on-the-fly and/or deeper sleep exit specification and can require a smaller inductor or more phases (the switching frequency can also have to be increased to keep the output ripple the same). For example, if using 32 pieces of 10 F 0805 MLC capacitors (CZ = 320 F), the fastest VID voltage change is the exit of deeper sleep, and VCORE change is 220 mV in 22 s with a setting error of 10 mV. Where K = 3.1, solving for the bulk capacitance yields
360 nH x 34.5 A - 320 F = 1.1 mF 27 mV x 1.150 V 2 x 2.1 m + 34.5 A
2 x 3.12 x (2.1 m )2 x 1.150 V 360 nH x 220 mV
x RDS(SF )
(17)
C x ( MIN )
C x ( MAX )
2 22 s x 1.150 V x 2 x 3.1 x 2.1 m - 1 - 320 F = 2.3 mF 1+ 220 mV x 360 nH
Using four 330 F Panasonic SP capacitors with a typical ESR of 6 m each yields CX = 1.32 mF with an RX = 1.5 m. One last check should be made to ensure that the ESL of the bulk capacitors (LX) is low enough to limit the high frequency ringing during a load change. This is tested using
Lx C z x RO 2 x Q 2 Lx 320 F x (2.1 m )2 x 2 = 2 nH
Knowing the maximum output thermal current and the maximum allowed power dissipation, users can find the required RDS(ON) for the MOSFET. For 8-lead SOIC or 8-lead SOIC compatible packaged MOSFETs, the junction to ambient (PCB) thermal impedance is 50C/W. In the worst case, the PCB temperature is 90C during heavy load operation of the notebook; a safe limit for PSF is 0.6 W at 120C junction temperature. Thus, for this example (32 A maximum thermal current), RDS(SF) (per MOSFET) is less than 9.6 m for two pieces of low-side MOSFET. This RDS(SF) is also at a junction temperature of about 120C; therefore, the RDS(SF) (per MOSFET) should be lower than 6.8 m at room temperature, giving 9.6 m at high temperature. Another important factor for the synchronous MOSFET is the input capacitance and feedback capacitance. The ratio of feedback to input needs to be small (less than 10% is recommended) to prevent accidental turn-on of the synchronous MOSFETs when the switch node goes high. The high-side (main) MOSFET has to be able to handle two main power dissipation components, conduction and switching losses. The switching loss is related to the amount of time it takes for the main MOSFET to turn on and off, and to the current and voltage that are being switched. Basing the switching speed on the rise and fall time of the gate driver impedance and MOSFET input capacitance, Equation 18 provides an approximate value for the switching loss per main MOSFETs
PS( MF ) = 2 x f SW x VCC x I O n x RG x MF x C ISS n MF n
(16)
where: Q is limited to the square root of 2 to ensure a critically damped system. In this example, LX is about 250 pH for the four SP capacitors, which satisfies this limitation. If the LX of the chosen bulk capacitor bank is too large, the number of ceramic capacitors may need to be increased if there is excessive ringing. Note that for this multimode control technique, an all-ceramic capacitor design can be used as long as the conditions of Equation 13, Equation 14, and Equation 15 are satisfied.
(18)
Rev. 0 | Page 23 of 32
ADP3207
where: nMF is the total number of main MOSFETs. RG is the total gate resistance (1.5 for the ADP3419 and about 0.5 for two pieces of typical high speed switching MOSFETs, making RG = 2 ). CISS is the input capacitance of the main MOSFET. The best thing to reduce switching loss is to use lower gate capacitance devices. The conduction loss of the main MOSFET is given by
PC ( MF ) I = D x O n MF 1 nx I R + x 12 n MF
2
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal PWM ramp. The value of this resistor is chosen to provide the best combination of thermal balance, stability, and transient response. Use this equation to determine a starting value
RR = AR x L 3 x AD x RDS x CR 0.2 x 360 nH 3 x 5 x 3.4 m x 5 pF = 282 k
(21)

2
x R DS( MF )
RR =
(19) where: AR is the internal ramp amplifier gain. AD is the current balancing amplifier gain. RDS is the total low-side MOSFET ON-resistance, CR is the internal ramp capacitor value. Another consideration in the selection of RR is the size of the internal ramp voltage (see Equation 22). For stability and noise immunity, keep this ramp size larger than 0.5 V. Taking this into consideration, the value of RR is selected as 280 k. The internal ramp voltage magnitude can be calculated using:
VR = A R x (1 - D ) x VVID R R x C R x f SW 0.2 x (1 - 0.061) x 1.150 V 280 k x 5 pF x 280 kHz = 0.55 V
where: RDS(MF) is the on-resistance of the MOSFET. Typically, for main MOSFETs, users want the highest speed (low CISS) device, but these usually have higher on-resistance. Users must select a device that meets the total power dissipation (0.6 W for a single 8-lead SOIC package) when combining the switching and conduction losses. For example, using an IRF7821 device as the main MOSFET (four in total; that is, nMF = 4), with about CISS = 1010 pF (max) and RDS(MF) = 18 m (max at TJ = 120C) and an IR7832 device as the synchronous MOSFET (four in total; that is, nSF = 4), RDS(SF) = 6.7 m (max at TJ = 120C). Solving for the power dissipation per MOSFET at IO = 32 A and IR = 10.7 A yields 420 mW for each synchronous MOSFET and 410 mW for each main MOSFET. One last consideration is the power dissipation in the driver for each phase. This is best described in terms of the QG for the MOSFETs and is given by the following equation:
f PDRV = SW x (nMF x QGMF + nSF x QGSF ) + I CC x VCC 2xn
(22)
VR =
(20)
where: QGMF is the total gate charge for each main MOSFET. QGSF is the total gate charge for each synchronous MOSFET. Also shown is the standby dissipation (ICC x VCC) of the driver. For the ADP3419, the maximum dissipation should be less than 300 mW, considering its thermal impedance is 220C/W and the maximum temperature increase is 50C. For this example, with ICC = 2 mA, QGMF = 14 nC and QGSF = 51 nC, there is 120 mW dissipation in each driver, which is below the 300 mW dissipation limit. See the ADP3419 data sheet for more details.
The size of the internal ramp can be made larger or smaller. If it is made larger, then stability and transient response improves, but thermal balance degrades. Likewise, if the ramp is made smaller, then thermal balance improves at the sacrifice of transient response and stability. The factor of three in the denominator of Equation 21 sets a minimum ramp size that gives an optimal balance for good stability, transient response, and thermal balance.
COMP Pin Ramp
There is a ramp signal on the COMP pin due to the droop voltage and output voltage ramps. This ramp amplitude adds to the internal ramp to produce the following overall ramp signal at the PWM input:
VRT = VR 2 x (1 - n x D ) 1 - nx f xC x R X SW O
(23)
For this example, the overall ramp signal is found to be 1.5 V.
Rev. 0 | Page 24 of 32
ADP3207
SETTING THE SWITCHING FREQUENCY FOR RPM MODE OPERATION OF PHASE 1
During the RPM mode operation of Phase 1, the ADP3207 runs in pseudo constant frequency, given that the load current is high enough for continuous current mode. While in discontinuous current mode, the switching frequency is reduced with the load current in a linear manner. When considering power conversion efficiency in light load, lower switching frequency is usually preferred for RPM mode. However, the VCORE ripple specification in the IMVP-6 sets the limitation for lowest switching frequency. Therefore, depending on the inductor and output capacitors, the switching frequency in RPM mode can be equal, larger, or smaller than its counterpart in PWM mode. A resistor between VRPM and RRPM pins sets the pseudo constant frequency as following:
R RPM = 2 x RT A x (1 - D) x VVID - 0. 5 k xR VVID + 1.0 V R R x C R x f SW
For the ADP3207, the maximum COMP voltage (VCOMP(MAX)) is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.0 V, and the current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V, and a RDS(MAX) of 3.8 m (low-side on-resistance at 150C) results in a per-phase limit of 85 A. Although this number seems high, this current level can only be reached with a absolute short at the output and the current-limit latch-off function shutting down the regulator before overheating occurs. This limit can be adjusted by changing the ramp voltage VR. However, users should not set the per-phase limit lower than the average per-phase current (ILIM/n). There is also a per-phase initial duty-cycle limit at maximum input voltage:
D LIM = D MIN x VCOMP( MAX ) - V BIAS VR
(27)
(24)
For this example, the duty-cycle limit at maximum input voltage is found to be 0.25 when D is 0.061.
where: AR is the internal ramp amplifier gain. CR is the internal ramp capacitor value. RR is an external resistor on the RAMPADJ pin to set the internal ramp magnitude. Because RR = 280 k, the following resistance sets up 300 kHz switching frequency in RPM operation.
RRPM = 2 x 237 k 1.150 V + 1.0 V x 0.2 x (1 - 0.061) x 1.150 - 500 = 80.6 k 280 k x 7 pF x 300 kHz
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3207 allows the best possible response of the regulator's output to a load change. The basis for determining the optimum compensation is to make the regulator and output decoupling appear as an output impedance that is entirely resistive over the widest possible frequency range, including dc, and equal to the droop resistance (RO). With the resistive output impedance, the output voltage droops in proportion with the load current at any load current slew rate. This ensures the optimal positioning and minimizes the output decoupling. With the multimode feedback structure of the ADP3207, users need to set the feedback compensation to make the converter output impedance work in parallel with the output decoupling. Several poles and zeros are created by the output inductor and decoupling capacitors (output filter) that need to be compensated for. A type-three compensator on the voltage feedback is adequate for proper compensation of the output filter. Equation 28 to Equation 36 is intended to yield an optimal starting point for the design; some adjustments can be necessary to account for PCB and component parasitic effects (see the Tuning Procedure for ADP3207).
CURRENT-LIMIT SETPOINT
To select the current-limit setpoint, we need to find the resistor value for RLIM. The current-limit threshold for the ADP3207 is set with a 1.7 V source (VLIM) across RLIM with a gain of 13 mV/A. RLIM can be found using the following equation:
RLIM = ALIM x VLIM I LIM x RO
(25)
For values of RLIM greater than 500 k, the current limit may be lower than expected, so some adjustment of RLIM may be needed. Here, ILIM is the average current limit for the output of the supply. In this example, if choosing 55 A for ILIM, RLIM is 190 k, which is close to a standard 1% resistance of 191 k. The per-phase current limit described earlier has its limit determined by the following:
I PHLIM VCOMP ( MAX ) - VR - VBIAS AD x RDS( MAX ) + IR 2
(26)
Rev. 0 | Page 25 of 32
ADP3207
The first step is to compute the time constants for all of the poles and zeros in the system
RE = n x RO + AD x RDS +
TA = C X x (RO - R ' ) +
RL x VRT 2 x L x (1 - n x D ) x VRT + n x C X x RO x VVID VID
(28) (29) (30)
L X RO - R' x RO RX
In a typical notebook system, the battery rail decouplings are MLCC capacitors or a mixture of MLCC capacitors and bulk capacitors. In this example, the input capacitor bank is formed by eight pieces of 10 F, and 25 V MLCC capacitors with a ripple current rating of about 1.5 A each.
SOFT TRANSIENT SETTING
As described in the Soft Transient section, during the soft transient, the slew rate of VCORE reference voltage change is controlled by the STSET pin capacitance. Because the timing of deeper sleep exit is critical, the STSET pin capacitance is set to satisfy the fast deeper sleep exit slew rate as
C STSET = 8 A 2 x SLEWRATEC 4 E
TB = (R X + R'-RO ) x C X
A x RDS VRT x L - D 2 x f SW TC = VVID x RE
TD =

(31) (32)
2 C X x C Z x RO C X x (RO - R ' ) + C Z x RO
(38)
where: R' is the PCB resistance from the bulk capacitors to the ceramics. RDS is the total low-side MOSFET on-resistance per phase. For this example, AD is 5, VRT = 1. 5 V, R' is approximately 0.4 m (assuming an 8-layer motherboard) and LX is 250 pH for the four Panasonic SP capacitors. The compensation values can be solved using the following:
CA = n x RO x TA RE x RB
where: 8 A is the source/sink current of the STSET pin. SLEWRATEC4E is the voltage slew rate during deeper sleep exit, defined as 10 mV/s in the IMVP-6 specification. CSTSET equals 400 pF, with the closest standard capacitance at 390 pF.
SELECTING THERMAL MONITOR COMPONENTS
For single-point hot spot thermal monitoring, simply set RTTSET1 equal to the NTC thermistor's resistance at the alarm temperature (see Figure 12). For example, if the VRTT alarm temperature is 100C using a Vishey thermistor (NTHS0603N011003J) with a resistance of 100 k at 25C, and 6.8 k at 100C, simply set RTTSET1 = RTH1(100C) to 6.8 k.
31 R VCC 5V
(33) (34) (35) (36)
RA =
TC CA
CB = CFB =
TB RB TD RA
RTTSET1 TTSENSE
VRTT
+
R
30
The standard values for these components are subject to the tuning procedure, as introduced in the CIN Selection and Input Current DI/DT Reduction section.
ADP3207
CTT
RTH1
Figure 12. Single-Point Thermal Monitoring
CIN SELECTION AND INPUT CURRENT DI/DT REDUCTION
In continuous inductor-current mode, the source current of the high-side MOSFET is approximately a square wave with a duty ratio equal to n x VOUT/VIN and an amplitude of 1-nth the maximum output current. To prevent large voltage transients, a low ESR input capacitor sized for the maximum rms current must be used. The maximum rms capacitor current happens at the lowest input voltage, and is given by:
I CRMS = D x I O x I CRMS 1 -1 nxD
Multiple-point hot spot thermal monitoring can be implemented as shown in Figure 13. If any of the monitored hot spots reaches alarm temperature, the VRTT signal is asserted. The following calculation sets the alarm temperature:
1/2+ RTTSET 1 = 1/2- VFD VREF VFD VREF RTH 1ALARMTEMPERATURE
(39)
(37)
where VFD is the forward drop voltage of the parallel diode. Because the forward current is very small, the forward drop voltage is very low (100 mV). Assuming the same 100C alarm temperature used in the single-spot thermal monitoring example, and the same Vishay thermistor, then Equation 39 leads to RTTSET = 7.37 k, whose closest standard resistor is 7.32 k (1%).
1 = 0.164 x 44 A x - 1 = 10.3 A 2 x 0.164
Rev. 0 | Page 26 of 32
ADP3207
5V
31
VCC RTTSET1 RTTSET2 RTTSETn
AC Loadline Setting
VFD
R VRTT
30
...
TTSENSE
ADP3207
R
RTH1
RTH2
RTHn
05782-014
VACDRP VDCDRP
Figure 13. Multiple-Point Thermal Monitoring
TUNING PROCEDURE FOR ADP3207
1. 2. Build the circuit based on compensation values computed from Equation 1 to Equation 39. Hook-up the dc load to the circuit. Turn the circuit on and verify operation. Check for jitter at no load and full load.
Figure 14. AC Loadline Waveform
11. Remove the dc load from the circuit and hook up the dynamic load. 12. Hook up the scope to the output voltage and set it to dc coupling with the time scale at 100 s/div. 13. Set the dynamic load for a transient step of about 40 A at 1 kHz with a 50% duty cycle. 14. Measure the output waveform (using the dc offset on scope to see the waveform, if necessary). Try to use the vertical scale of 100 mV/div or finer. 15. Users should see a waveform that similar to the one in Figure 15. Use the horizontal cursors to measure VACDRP and VDCDRP as shown. Do not measure the undershoot or overshoot that occurs immediately after the step. 16. If the VACDRP and VDCDRP are different by more than a couple of mV, use the following to adjust CCS (note that users may need to parallel different values to get the right one due to the limited standard capacitor values available. It is also wise to have locations for two capacitors in the layout for this):
C CS ( NEW ) = C CS (OLD ) x V ACDRP VDCDRP
DC Loadline Setting
3. 4. Measure the output voltage at no load (VNL). Verify that it is within tolerance. Measure the output voltage at full load and at cold (VFLCOLD). Let the board set for a ~10 minutes at full load and measure the output (VFLHOT). If there is a change of more than a few millivolts, then adjust RCS1 and RCS2 using Equation 40 and Equation 41.
RCS 2( NEW ) = RCS 2(OLD ) x VNL - VFLCOLD VNL - VFLHOT
(40)
5. 6.
Repeat Step 4 until cold and hot voltage measurements remain the same. Measure output voltage from no load to full load using 5 A steps. Compute the load line slope for each change and then average it to get the overall load line slope (ROMEAS). If ROMEAS is off from RO by more than 0.05 m, use the following to adjust the RPH values:
R PH ( NEW ) = R PH (OLD ) x ROMEAS RO
05782-012
The number of hot spots monitored is not limited. The alarm temperature of each hot spot can be set differently by playing different RTTSET1, RTTSET2, RTTSETn.
(42)
7.
(41)
17. Repeat Steps15 and Step 16. Repeat adjustments if necessary. Once complete, do not change CCS for the rest of the procedure. 18. Set dynamic load step to maximum step size. Do not use a step size larger than needed. Verify that the output waveform is square, which means VACDRP and VDCDRP are equal. Note: Make sure that the load step slew rate and turn-on are set for a slew rate of ~150 A/s to 250 A/s (for example, a load step of 50 A should take 200 ns to 300 ns) with no overshoot. Some dynamic loads have an excessive turn-on overshoot if a minimum current is not set properly (this is an issue if you are using a VTT tool).
8. 9.
Repeat Step 6 and Step 7 to check load line and repeat adjustments if necessary. Once complete with dc load line adjustment, do not change RPH, RCS1, RCS2, or RTH for the rest of procedure.
10. Measure output ripple at no load and full load with a scope to make sure it is within specification.
Rev. 0 | Page 27 of 32
ADP3207
Initial Transient Setting
19. With dynamic load still set at the maximum step size, expand the scope time scale to see 2 s/div to 5 s/div. A waveform that has two overshoots and one minor undershoot can result (see Figure 15). Here, VDROOP is the final desired value.
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal performance of a switching regulator in a PC system.
General Recommendations
For effective results, at least a four-layer PCB is recommended. This allows the needed versatility for control circuitry interconnections with optimal placement, power planes for ground, input and output power, and wide interconnection traces in the rest of the power delivery current paths. Note that each square unit of 1 ounce copper trace has a resistance of ~0.53 m at room temperature. When high currents need to be routed between PCB layers, vias should be used liberally to create several parallel current paths so that the resistance and inductance introduced by these current paths are minimized, and the via current rating is not exceeded. If critical signal lines (including the output voltage sense lines of the ADP3207) must cross through power circuitry, then a signal ground plane should be interposed between those signal lines and the traces of the power circuitry. This serves as a shield to minimize noise injection into the signals at the expense of making signal ground a bit noisier. An analog ground plane should be used around and under the ADP3207 for referencing the components associated with the controller. Tie this plane to the nearest output decoupling capacitor ground. It should not be tied to any other power circuitry to prevent power currents from flowing in it. The best location for the ADP3207 is close to the CPU corner where all the related signal pins are located: VID0 to VID6, PSI, VCCSENSE, and VSSSENSE. The components around the ADP3207 should be located close to the controller with short traces. The most important traces to keep short and away from other traces are the FB and CSSUM pins (refer to Figure 10 for more details on layout for the CSSUM node.) The MLCC for the VCC decoupling should be placed as close to the VCC pin as possible. In addition, the noise filtering cap on the TTSENSE pin should also be as close to that pin as possible. The output capacitors should be connected as closely as possible to the load (or connector) that receives the power (for example, a microprocessor core). If the load is distributed, then the capacitors should also be distributed, and generally in proportion to where the load tends to be more dynamic.
VDROOP
VTRAN1
VTRAN2
05782-015
Figure 15. Transient Setting Waveform, Load Step
20. If both overshoots are larger than desired, make the following adjustments in the order they appear. Note that if these adjustments do not change the response, then users are limited by the output decoupling. In addition, check the output response each time a change is made, as well as the switching nodes to make sure they are still stable. a. b. c. Make ramp resistor larger by 25% (RRAMP). For VTRAN1, increase CB or increase switching frequency. For VTRAN2, increase RA and decrease CA both by 25%.
21. For load release (see Figure 16), if VTRANREL is larger than the IMVP-6 specification, there is not enough output capacitance. Either more capacitance is needed or the inductor values needed to be smaller. If the inductors are changed, then start the design over using Equation 1 to Equation 39 and this tuning guide.
VTRANRE L
VDROOP
Figure 16. Transient Setting Waveform, Load Release
05782-016
Rev. 0 | Page 28 of 32
ADP3207
Power Circuitry
Avoid crossing any signal lines over the switching power path loop. This path should be routed on the PCB to encompass the shortest possible length in order to minimize radiated switching noise energy (that is, EMI) and conduction losses in the board. Failure to take proper precautions often results in EMI problems for the entire PC system as well as noise-related operational problems in the power converter control circuitry. The switching power path is the loop formed by the current path through the input capacitors and the power MOSFETs, including all interconnecting PCB traces and planes. The use of short and wide interconnection traces is especially critical in this path for two reasons: it minimizes the inductance in the switching loop, which can cause high energy ringing, and it accommodates the high current demand with minimal voltage loss. Whenever a power-dissipating component (for example, a power MOSFET) is soldered to a PCB, the liberal use of vias, both directly on the mounting pad and immediately surrounding it, is recommended. Two important reasons for this are: improved current rating through the vias, and improved thermal performance from vias extended to the opposite side of the PCB where a plane can more readily transfer the heat to the air. Make a mirror image of any pad being used to heat sink the MOSFETs on the opposite side of the PCB to achieve the best thermal dissipation to the air around the board. To further improve thermal performance, the largest possible pad area should be used. The output power path should also be routed to encompass a short distance. The output power path is formed by the current path through the inductor, the output capacitors, and the load. For best EMI containment, use a solid power ground plane as one of the inner layers extending fully under all the power components. It is important for conversion efficiency that MOSFET drivers, such as ADP3419, are placed as close to the MOSFETs as possible. Thick and short traces are required between the driver and MOSFET gate, especially for the SR MOSFETs. Ground the MOSFET driver's GND pin through immediately close vias.
Signal Circuitry
The output voltage is sensed and regulated between the FB pin and the FBRTN pin, which connects to the signal ground at the load. To avoid differential mode noise pickup in the sensed signal, the loop area should be small. Thus, route the FB and FBRTN traces adjacent to each other atop the power ground plane back to the controller. To filter any noise from the FBRTN trace, using a 1000 pF MLCC is suggested. It should be placed between the FBRTN pin and local ground and as close to the FBRTN pin as possible. Connect the feedback traces from the switch nodes as close as possible to the inductor. The CSREF signal should be Kelvin connected to the center point of the copper bar, which is the VCORE common node for the inductors of all phases. In the back side of the ADP3207 package, a metal pad can be used as the device heat sink. In addition, running vias under the ADP3207 is not recommended because the metal pad can cause shorting between vias.
Rev. 0 | Page 29 of 32
ADP3207 OUTLINE DIMENSIONS
6.00 BSC SQ 0.60 MAX 0.60 MAX
31 30 40 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
5.75 BCS SQ
0.50 BSC 0.50 0.40 0.30
EXPOSED PAD
(BOT TOM VIEW)
4.25 4.10 SQ 3.95
10
21 20
0.25 MIN 4.50 REF
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM
EXPOSED PADDLE CAN BE GROUNDED.
1.00 0.85 0.80
SEATING PLANE
0.30 0.23 0.18
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 17. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 6 mm x 6 mm Body, Very Thin Quad (CP-40) Dimensions shown in millimeters
ORDERING GUIDE
Model ADP3207JCPZ-RL1
1
Temperature Range 0C to 100C
Package Description 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option CP-40
Order Quantity 2,500
Z = Pb-free part.
Rev. 0 | Page 30 of 32
ADP3207 NOTES
Rev. 0 | Page 31 of 32
ADP3207 NOTES
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05782-0-1/06(0)
Rev. 0 | Page 32 of 32

▲Up To Search▲

Price & Availability of ADP3207

	To Download ADP3207 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .